Analog-to-digital converters (ADCs) are widely used in applications where an analog signal (e.g., voltage, current, temperature, pressure) must be converted to a digital signal (digital value) for processing by digital circuitry. In battery-powered portable equipment, especially wireless communications devices, ultra-low power ADCs are required to minimize battery drain.
Some of the more common architectures for ADCs include flash, successive approximation, sigma-delta, integrating, cyclic (also known as algorithmic), and pipelined. Each of these architectures offers a range of values within important operating parameters of speed, accuracy, and power. Each also offers trade-offs with regard to circuit size.
For example, successive approximation based ADCs with passive sampling usually achieve very low power operation since they avoid the use of active analog amplifiers. However, the speed and resolution of such converters is limited by mismatches in capacitor values and comparator accuracy. Redundancy-based digital correction algorithms may be used to increase speed and resolution of an ADC while reducing the mismatch and accuracy requirements. However, traditional digital correction algorithms are not directly applicable to the successive approximation ADC architecture because the residual signals must typically be amplified between conversion cycles in a redundancy-based digital correction scheme.